The invention relates to part of a synchronization device for a synchronous digital message transmission system for producing a synchronous output signal out of a digital input signal in accordance with the topic of claim 1 and a process for producing a synchronous output signal in accordance with the topic of claim 8.
A part of a synchronization device for SDH or SONET systems is known from the conference article xe2x80x9cSONET/SDH Pointer Processor Implementationxe2x80x9d by M. Klein and R. Urbansky, 1994 IEEE GLOBECOM Communications: The Global Bridge, San Francisco, Nov. 28-Dec. 2, 1994, pp. 655-660, such systems producing a synchronous output signal from plesiochronous or pseudosynchronous digital input signals. In addition, the input signals are written bit by bit with a write clock into buffer memory and read again with a read clock in order to form the synchronous output signal. Under this application, the read clock has to be synchronized to a reference clock pulse of the message transmission system, specifically with the precision set forth in ITU-T G.813 for SDH systems of xc2x14.6 ppm.
The output signals produced thus are transported over the message transmission system and reintegrated at the other end, using a desynchronization device, into their original plesiosynchronous or pseudosynchronous message signals. A difficulty that can emerge because of transmission is that low-frequency phase fluctuations can be added up that are caused by the intermediary saving in different buffer memories of the message transmission system. Such low-frequency phase fluctuations are characterized as wanders and can lead to exceeding buffer memory and any data loss tied to this. The conference article suggests avoiding such wanders by modulating the decision level of the pointer processor with a constant frequency. This wave modulation is however technologically expensive since all network elements have to be changed to deviate from the standardization. In addition, the wave modulation leads to a considerable increase of jitter in the message transmission system.
The task of the invention is to give a synchronization device for a synchronous digital message transmission system as well as a process for producing a synchronous output signal through which the low-frequency phase fluctuations are minimized in another, technologically less expensive fashion.
The task is solved with respect to the synchronization device through the characteristics of claim 1 and with respect to the process through the characteristics of claim 8. Advantageous reconfigurations can be interpolated from the dependent claims.
Beside the lessening and avoidance of wanders, another advantage of the invention is that both the synchronization device as well as the desynchronization device on the other end of the transmission leg and intermediately switched network elements of the synchronous digital message transmission system come out with smaller buffer memories than until now. Another advantage of the invention is that the duration of message signals through the message transmission system is diminished whenever the write clock is less than the read clock because the filling level of all buffer memory of the transmission leg then lies at the bottom limit. Another advantage of the invention is that the synchronization device in accordance with the invention is compatible with existing message transmission systems.
With another especially advantageous construction of the invention as under claim 7, an input signal is divided and packaged in a parallel fashion into several subassemblies of synchronous transport modules. These several subassemblies are saved intermediately with the write clock in the buffer memory and with the higher or lower read clock in such a way that several synchronous output signals are created. The particular advantage of this additional construction is that now input signals, for example ATM signals (asynchronous transport mode) or digitized video signals, can be processed that would explode the transportation capacity of a single virtual container. Through intermediary saving with the write clock in accordance with the inventionxe2x80x94the write clock being lower than the read clockxe2x80x94phase fluctuations, i.e. differences in transmission time, of the different virtual containers can be avoided. Thus, a desynchronization device at the other end of the synchronous message transmission system achieves the simple integration of the transported portions packaged in several subassemblies that are from the original input signal put back into their original form.